The implementation of a transceiver capable of reducing power consumption in wireless communication and being flexibly used in many applications has become a recent issue. To meet this issue, a variety of FSK methods have been proposed.
In order to implement FSK in a transmitter, an analog phase-locked loop apparatus is commonly used. When the analog phase-locked loop circuit is used, a variety of buffers for appropriately transferring signals are required because an analog signal level is an important factor.
This may become a cause of increased current consumption. Furthermore, since almost all circuit blocks must be redesigned when a process is varied or scaled down because the analog phase-locked loop is very sensitive to a process, the time and cost are increased.
Furthermore, there is a limitation to a part that reduces in-band noise from among the phase noise of the analog phase-locked loop circuit. In general, the channel of the oscillating frequency of the analog phase-locked loop circuit is varied using a divider and a counter. In this case, a lot of current is consumed because the blocks must operate at a high speed.